Inverted isolation formed with spacers

US6891229B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Andrea Franke · Oakland, US
• Jonathan Cobb · Austin, US
• John M. Grant · Vancouver, US
• Al T. Koh · Cedar Park, US
• Yeong-Jyh T. Lii · Austin, US
• Bich-Yen Nguyen · Austin, US
• Anna Phillips · Colleyville, US

Key dates

• Filing date: Apr 30, 2003
• Grant date: May 10, 2005
• Expiry date: Jul 24, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/762
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a semiconductor device so as to provide the device inverted isolation trenches with convex sidewalls. Initially, a plurality of composite isolation posts (50, 51) are formed on a substrate (40) through successive deposition, lithography, and etching steps. The posts comprise a bottom layer (501, 502) of silicon dioxide and an overlying etch-stop layer of silicon nitride (502, 512). An insulating material (60) is then deposited over the isolation posts and areas of the substrate. Isolation structures (70,71) are established by etching the insulating material to form convex sidewall spacers (701,702, 711, 712) at the vertical walls of the isolation posts. Active areas (80) between spacers are filled with semiconductor material. In an embodiment, a strained cap layer (101) may be imposed on the active areas. The strained cap layer has a lattice constant that is different from the lattice constant of the semiconductor material.