Method of erasing information in non-volatile semiconductor memory device
US6891760B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 2002 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jul 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A potential of −3V is applied to a control gate electrode, a potential of 5V is applied to a pair of impurity regions and a potential of 3V is applied to a semiconductor substrate in a non-volatile semiconductor memory device. Accordingly, electrons existing on one impurity region side in a silicon nitride film move toward that impurity region, and electrons existing on the other impurity region side move toward that impurity region. Furthermore, electrons existing in that part (middle part) of the silicon nitride film which is positioned immediately above a region approximately at the middle point between one impurity region and the other impurity region move toward the semiconductor substrate. Therefore, MPE (Miss Placed Electron) is no longer caused in the non-volatile semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.