Low via resistance system
US6893962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2003 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Sep 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2855
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage. The plasma within the ion metal plasma deposition chamber is energized at a second power for a second length of time, after which the substrate is removed from the ion metal plasma deposition chamber. Finally, a third liner layer of titanium nitr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.