IC with comparator receiving expected and mask data from pads
US6894308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Apr 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Test circuits located on semiconductor die enable a tester to scan test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal scheme whereby the tester transmits response test commands to the test circuits, using an expected data signal on one output pad and a mask data signal on another pad, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal scheme provides scan testing of die and ICs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.