Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor
US6894330B2 · kind B2 · utility
4Cited by
4References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 14, 2001 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Jan 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.