Vertical bipolar transistor

US6894367B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Peter Nelle · Munich, DE
• Matthias Stecher · Munich, DE

Key dates

• Filing date: Feb 14, 2003
• Grant date: May 17, 2005
• Expiry date: Apr 27, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/60

Abstract

A vertical bipolar transistor has a J-FET incorporated in an epitaxial layer. The pinch-off voltage of the J-FET is less than the collector-emitter breakdown voltage of a bipolar transistor without the J-FET. This results in a considerable increase in the collector-emitter breakdown voltage up to 30 V or more being possible without having to except limitations with regard to dielectric strength and on resistivity