Non-volatile memory cell sensing circuit, particularly for low power supply voltages and high capacitive load values
US6894934B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2003 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Dec 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sensing circuit for a memory cell includes a first bias current generator connected between a first voltage reference and a first inner circuit node, and a second reference current generator connected to the first voltage reference. A comparator having a first input terminal is connected to a comparison circuit node that is connected to the second reference current generator, a second input terminal is connected to a circuit node that is connected to the first inner circuit node, and an output terminal forms an output terminal of the sensing circuit. A cascode-configured bias circuit is connected between the inner circuit node and a matching circuit node. The cascode-configured bias circuit is also connected to a second voltage reference. A current/voltage conversion stage is connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.