Reordering and flushing commands in a computer memory subsystem
US6895482B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1999 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Sep 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0659
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution. Memory commands of that type are selected for execution each subsequent cycle until a valid memory command of that type is no longer available, or until a predetermined number has been executed, or until a memory command of another type has higher priority. If an address dependency exists between memory commands of different …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.