Method of forming well for CMOS imager
US6897082B2 · kind B2 · utility
43Cited by
4References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Aug 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/014
Abstract
A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.