Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode

US6897095B1 · kind B1 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Olubunmi O. Adetutu · Austin, US
• Srikanth B. Samavedam · Austin, US
• Bruce E. White · Round Rock, US

Key dates

• Filing date: May 12, 2004
• Grant date: May 24, 2005
• Expiry date: May 12, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0181

Abstract

A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.