Process for planarizing array top oxide in vertical MOSFET DRAM arrays
US6897108B2 · kind B2 · utility
2Cited by
8References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 14, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Dec 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0383
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.