Methods of forming a transistor having a recessed gate electrode structure
US6897114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jun 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/668
Abstract
In manufacturing a recessed gate transistor, a channel implantation and a source/drain implantation are performed by means of a single implantation mask prior to the formation of a gate opening. Thereafter, the gate opening is formed to a depth that extends substantially to the channel implant so that raised drain and source regions are created which are substantially even with the gate electrode formed in the gate opening. Consequently, expensive and complex epitaxial growth steps can be avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.