Method of forming integrated circuitry and method of forming shallow trench isolation in a semiconductor substrate
US6897120B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 2001 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Aug 1, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming integrated circuitry includes forming a silicon nitride comprising layer over a semiconductor substrate. At least a portion of the silicon nitride comprising layer is etched using an etching chemistry comprising ammonia and at least one fluorocarbon. A method of forming shallow trench isolation in a semiconductor substrate includes depositing a silicon nitride comprising layer over a bulk semiconductor substrate. A photoresist comprising masking layer is formed over the silicon nitride comprising layer. The photoresist comprising masking layer is patterned effective to form a plurality of shallow trench mask openings therethrough. The silicon nitride comprising layer is etched through the mask openings substantially selectively relative to the photoresist using an etching chemistry comprising ammonia and at least one fluorocarbon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.