Methods of forming backside connections on a wafer stack
US6897125B2 · kind B2 · utility
59Cited by
15References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Sep 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The vias used for the backside connections are formed on a side of the first wafer along with an interconnect structure, and the backside connections are formed on an opposing side of the first wafer using these vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.