Patent · US Expired

Controllable ovanic phase-change semiconductor memory device

US6897467B2 · kind B2 · utility

52Cited by
32References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 17, 2003
Grant dateMay 24, 2005
Priority date
Expiry dateMar 30, 2023

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C2213/52

Abstract

An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same, are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.