High density semiconductor memory cell and memory array using a single transistor having a buried N+ connection
US6898116B2 · kind B2 · utility
48Cited by
63References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 2, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Oct 2, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, the row wordline is formed from a buried N+ layer allowing for higher density integration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.