Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations
US6898726B1 · kind B1 · utility
46Cited by
13References
75Claims
0Family size
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Key dates
| Filing date | Nov 15, 2000 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jun 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock system for a data bus, e.g., a memory bus system, provides a write data (WCLK) clock signal in one direction on a bus and a data read (RCLK) clock signal in an opposite direction on the bus. A predetermined phase relationship between said WCLK and RCLK clock signals is set at a predetermined location on the data bus to ensure that all memory subsystems connected to the bus receive the WCLK and RCLK signals with appropriate timing to ensure proper operation of the memory subsystems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.