Epitaxially coated semiconductor wafer and process for producing it

US6899762B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Guido Wenski · Burghausen, DE
• Wolfgang Siebert · Mehring, DE
• Klaus Messmann · Burghausen, DE
• Gerhard Heier · Burghausen, DE
• Thomas Altmann · Burghausen, DE
• Martin Fürfanger · San Jose, US

Key dates

• Filing date: Mar 28, 2003
• Grant date: May 31, 2005
• Expiry date: Jun 14, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T428/24355
• WIPO field: Machine tools
• WIPO sector: Mechanical engineering

Abstract

A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface. In the semiconductor wafer, the epitaxial layer has a maximum local flatness value SFQRmax of less than or equal to 0.13 μm and a maximum density of 0.14 scattered light centers per cm2. The front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 μm×1 μm reference area. Furthermore, there is a process for producing the semiconductor wafer. The process includes the following process steps: (a) as a single polishing step, simultaneous polishing of the front surface and of the back surface of the semiconductor wafer between rotating polishing plates while an alkaline polishing slurry is being supplied, the semiconductor wafer lying in a cutout of a carrier whose thickness is dimensioned to be 2 to 20 μm less than the thickness of the semiconductor wafer after the latter has been polished; (b) simultaneous treatment of the front surface and of the back surface of the semiconductor wafer between rotating polishing plates while a liquid contai…