Apparatus and method for enhanced voltage contrast analysis
US6900065B2 · kind B2 · utility
1Cited by
2References
45Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 19, 2002 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Dec 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/311
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and a method for electrically testing a semiconductor wafer, the method including: (i) depositing electrical charges at certain points of a test pattern; (ii) scanning at least a portion of the test pattern such as to enhance charge differences resulting from defects; and (iii) collecting charged particles emitted from the at least scanned portion as a result of the scanning, thus providing an indication about an electrical state of the respective test structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.