Method of etching variable depth features in a crystalline substrate
US6900133B2 · kind B2 · utility
7Cited by
19References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2002 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Mar 17, 2023 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0132
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Disclosed herein is an easy and well-integrated method of etching features to different depths in a crystalline substrate, such as a single-crystal silicon substrate. The method utilizes a specialized masking process and takes advantage of a highly selective etch process. The method provides a system of interconnected, variable depth reservoirs and channels. The plasma used to etch the channels may be designed to provide a sidewall roughness of about 200 nm or less. The resulting structure can be used in various MEMS applications, including biomedical MEMS and MEMS for semiconductor applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.