Enhanced debug scheme for LBIST
US6901546B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2001 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Aug 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.