Process for forming dual metal gate structures

US6902969B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Olubunmi O. Adetutu · Austin, US
• Hsing-Huang Tseng · Austin, US
• Wei E. Wu · Austin, US

Key dates

• Filing date: Jul 31, 2003
• Grant date: Jun 7, 2005
• Expiry date: Aug 7, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177

Abstract

A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.