Sputter etch methods
US6903026B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 2004 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Jun 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32131
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sputter etch method in the semiconductor fabrication is disclosed. A sputter etch method for etching a layer on a semiconductor substrate in a chamber by RF plasma, includes loading a substrate for conditioning into the chamber, depositing a metal coating layer on the inside wall of the chamber by sputter etching the substrate for conditioning in the chamber, unloading the substrate for conditioning from the chamber, loading the semiconductor substrate with the layer, and etching the layer on the semiconductor substrate. Accordingly, the sputter etch method can enhance a reliability for a fabrication process of a semiconductor device under the environment of the substantial decrease in impurity falling probability. In other words, the impurity falling probability can be decreased by coating a metal layer on the wall of the sputter etch chamber employing a wafer on which a barrier metal layer is deposited right before a main lot in a sputter etch process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.