System and method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
US6903384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Jan 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6733
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method comprises: forming a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forming a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forming a layer of strained-Si overlying the first and second SiGe layers; forming a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forming an n-well in the substrate and the overlying first layer of SiGe; forming a p-well in the substrate and the overlying second layer of SiGe; forming channel regions, in the strained-Si, and forming PMOS and NMOS transistor source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.