Silicon rich barrier layers for integrated circuit devices
US6903425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2002 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Feb 15, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.