Semiconductor device capable of preventing a pattern collapse
US6903428B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Jul 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is disclosed that is capable of preventing a pattern collapse phenomenon in a cell edge area in which a pattern is more fragile. The semiconductor device has a lower pattern density in an edge area than in a central area of a wafer and includes a plurality of bar-type patterns allocated at a predetermined distance in the central area of the wafer; a plurality of dummy patterns formed in the edge area; and a plurality of a connection pattern for coupling at least two of the bar-type patterns to each other, wherein the connection patterns of the plurality of dummy patterns offset or staggered with respect to each other to form a disconnected zigzag pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.