Memory with charge storage locations and adjacent gate structures
US6903967B2 · kind B2 · utility
29Cited by
24References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | May 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.