Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of substrate current
US6903979B1 · kind B1 · utility
7Cited by
3References
7Claims
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Key dates
| Filing date | Sep 17, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Dec 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of programming a PMOS stacked gate memory cell is provided that utilizes the correlation between injection current and substrate current during the programming cycle to provide a feedback correction to the control gate of the memory cell to compensate for the negative potential shift on the floating gate as a result of its charging time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.