Bit line segmenting in random access memories
US6903982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2002 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Jul 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory circuit and corresponding method for segmenting bit lines are provided, where the integrated memory circuit includes a sense amplifier, a layered bit line in signal communication with the sense amplifier, several segment pass transistors in signal communication with the layered bit line, several segmented bit lines, each in signal communication with a corresponding one of the several segment pass transistors, respectively, several memory cell pass transistors in signal communication with one of the several segmented bit lines, and a plurality of memory cell capacitors, each in signal communication with a corresponding one of the plurality of memory cell transistors, respectively; and where the corresponding method for segmenting bit lines includes receiving a memory cell address, activating a memory cell pass transistor with a wordline corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a segmented bit line through the memory cell transistor, activating a segment pass transistor corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a layered bit line thro…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.