Method and system for placing logic nodes based on an estimated wiring congestion
US6904584B2 · kind B2 · utility
10Cited by
14References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 2002 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Jan 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for placing logic nodes based on an estimated wiring congestion are provided. Specifically, under the present invention, relative probabilities for potential implementations of wiring interconnects between logic nodes are determined. Then, for each edge between adjacent bins, a total of corresponding relative probabilities is compared to a wiring availability. Based on the comparison, the logic nodes can be placed within wiring constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.