Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US6906360B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2003 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Sep 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.