Method for fabricating a semiconductor structure with an encapsulation of a filling which is used for filling trenches

US6908831B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Lincoln O'Riain · Dresden, DE
• Jorg Radecker · Dresden, DE

Key dates

• Filing date: Oct 15, 2004
• Grant date: Jun 21, 2005
• Expiry date: Oct 15, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76224
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for encapsulating a filling in a trench of a semiconductor substrate includes providing a first barrier layer in a trench and a second barrier layer disposed above the first barrier layer. The trench is filled with a filling, which is subsequently etched back in an upper trench section, so that a hole is produced and a filling residue remains in a lower trench section. Subsequently, a non-conformal cover layer is provided in an upper trench section, so that the cover layer of a bottom region has a first thickness greater than a second thickness of a wall region of the cover layer. The cover layer and the second barrier layer are isotropically etched-back and removed from the upper trench section, and the first barrier layer remains. The bottom region remains covered resulting in the filling residue being encapsulated by the first barrier layer and the residual cover layer.