Nonplanar device with stress incorporation layer and method of fabrication
US6909151B2 · kind B2 · utility
187Cited by
9References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Jun 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/798
Abstract
A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.