Patent · US Expired

Device and method for reducing the number of addresses of faulty memory cells

US6910161B2 · kind B2 · utility

3Cited by

1References

2Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Justus Kuhn · Birkenfeld, DE
Peter Weitz · Sauerlach, DE

Key dates

Filing date	Dec 14, 2001
Grant date	Jun 21, 2005
Priority date	—
Expiry date	Apr 28, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/814
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and a device for reducing addresses of faulty memory cells compare addresses of faulty memory cells, as first fault addresses, with addresses of word lines or bit lines which are to be completely repaired, these addresses are referred to as second fault addresses. If the first fault address corresponds to the second fault address, the first fault address is deleted and not further processed. In a second comparison, it is determined, by reference to the number of non-deleted first fault addresses, whether an address of a word line or bit line is used as a new second fault address for the first comparison method. The number of addresses of faulty memory cells are thus reduced.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.