Methods for fabricating MRAM device structures
US6911156B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2003 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Oct 1, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.