Flash memory structure and operating method thereof
US6914826B2 · kind B2 · utility
8Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2004 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | May 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory structure is provided. The flash memory structure includes a P-type substrate, a deep N-well set up within the P-type substrate, a P-well set up within the deep N-well, a pair of gate structures set up over the substrate, a select gate set up between the pair of gate structure and N-type source/drain regions in the P-well on each side of the gate structure. Since each pair of neighboring gate structure uses a common gate, the level of integration of device can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.