DRAM memory with a shared sense amplifier structure
US6914837B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2004 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Jan 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as differential amplifiers. In an exemplary embodiment, a one of four bit line pairs of the two adjacent cell blocks can be selected for connection to a sense amplifier at any one time using respective isolation transistor pairs, in response to a connection control signal fed to the latter. A signal sent on a word line coupled to a memory cell associated with the selected bit line pair, provides access to the memory cell by the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.