Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing
US6916682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2001 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Nov 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package device (10, 100) has one integrated circuit (22, 122) in a cavity (20, 120) in a package substrate (12, 122) and electrically coupled to one side (50, 150) of the package substrate. A second integrated circuit (32, 132) is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit (38, 138) or more may be mounted on the second integrated circuit. Pads (16, 116, 116) useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.