Mixed-mode process
US6916700B1 · kind B1 · utility
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5References
22Claims
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Key dates
| Filing date | Jan 15, 2004 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Jan 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
A mixed-mode process introduces a hard mask layer. Due to the introduced hard mask layer made of non-resist material formed over devices, performance of a formed capacitor is protected from effects of an implantation process such as source/drain implantation. A self-aligned silicide (salicide) process for a MOSFET transistor can also be performed. Thus, production efficiency and performance of an IC product formed by the mixed-mode process can be improved. Moreover, the number of required fabrication steps is reduced and cost savings can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.