High coupling floating gate transistor
US6916707B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 2003 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Dec 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
The present invention provides methods of fabricating floating gate transistors. One method includes forming laterally spaced source and drain regions to define a channel therebetween, forming a first floating gate portion above the channel region, the first floating gate portion extending in a general horizontal direction, forming spacers over the first floating gate portion to define an exposed region on the first floating gate portion, forming a contact coupled to the first floating gate portion at the exposed region, the contact extending vertically above the first portion, forming a second floating gate portion coupled to the contact, the second floating gate portion extending in a general vertical direction, and forming a control gate adjacent to the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.