Patent · US Expired

Integrated memory and method for operating it

US6917549B2 · kind B2 · utility

1Cited by

8References

8Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Manfred Proll · Dorfen, DE
Stephan Schröder · Birkenfeld, DE
Heinz Neubauer
Evangelos Stavrou · Munich, DE

Key dates

Filing date	Jan 20, 2004
Grant date	Jul 12, 2005
Priority date	—
Expiry date	Jan 20, 2024

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4097
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated memory has a memory cell array having word lines and bit lines. The bit lines are organized in bit line pairs. The bit lines of the bit line pairs cross one another at a crossing location and run parallel to one another. A sense amplifier is connected to one of the bit line pairs at one end. Two precharge circuits are provided. One precharge circuit is arranged on a side of the crossing location and the other precharge circuit is arranged on a side of the crossing location. The precharge circuit facing the sense amplifier is arranged at a first distance from the crossing location and at a second distance from the sense amplifier. The RC constant of the bit lines, which is effective during the precharge operation, is reduced, so that the time period required for a precharge operation is reduced.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.