Superjunction device and process for its manufacture
US6919241B2 · kind B2 · utility
2Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2003 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Jul 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
A process to make a low voltage (under 200 volts) superjunction device employs spaced P type implants into the generally central depth region of an epitaxially formed N layer. The wafer is then placed in a diffusion furnace and the spaced implants are driven upward and downward by 4 to 8 microns to form spaced P pylons in an N type epitaxial body. MOSgated structures are then formed atop each of the P pedestals. The total P charge of each pedestal is at least partially matched to the total N charge of the surrounding epitaxial material. The initial implant may be sandwiched between two discrete epitaxial layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.