High-voltage silicon controlled rectifier structure with improved punch through resistance
US6919588B1 · kind B1 · utility
6Cited by
8References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 27, 2003 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Aug 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/251
Abstract
When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.