Programming method of the memory cells in a multilevel non-volatile memory device
US6920066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2003 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Sep 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5628
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming a non-volatile memory device of the multi-level type, includes a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.