Method for making trench MIS device with reduced gate-to-drain capacitance

US6921697B2 · kind B2 · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Mohamed N. Darwish · Campbell, US
• Frederick P. Giles · San Jose, US
• Kam Hong Lui · Santa Clara, US
• Kuo-In Chen · Los Altos, US
• Kyle Terrill · Santa Clara, US

Key dates

• Filing date: Oct 3, 2002
• Grant date: Jul 26, 2005
• Expiry date: Oct 3, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/157

Abstract

Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.