Data strobe synchronization circuit and method for double data rate, multi-bit writes
US6922367B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2003 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Jul 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.