Verifying proximity of ground vias to signal vias in an integrated circuit
US6922822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2002 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Feb 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for verifying the proximity of ground vias to signal vias in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a ground via within a predetermined threshold distance of each specified signal via in the package design. The proximity verifier may notify the package designer of any signal vias which are not sufficiently close to ground vias, such as by providing visual indications of such signal vias in a graphical representation of the package design displayed on a display monitor. In response, the package designer may modify the package model to ensure that all signal vias are sufficiently close to ground vias. The proximity verifier may be implemented as a design rule which may be executed automatically and in real-time by the package design tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.