Self-aligned gate formation using polysilicon polish with peripheral protective layer
US6924220B1 · kind B1 · utility
4Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Oct 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/42
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of protecting a peripheral region, by forming a protective mask over the peripheral area, during polysilicon polishing while forming self-aligned polysilicon gates in flash memory circuits. In one aspect, the protective mask is formed over a substantial area of the Peripheral region. In another aspect, the protective mask is formed over a substantial area of an active part of the peripheral region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.