Semiconductor process and composition for forming a barrier material overlying copper
US6924232B2 · kind B2 · utility
15Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Sep 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electroless plating process for forming a barrier film such as a cobalt tungsten boron film on copper interconnects lines of semiconductor wafers uses a plating bath of morpholine borane which provides higher thermal stability and range, allowing for greater compatibility with low k dielectric materials. Mixed chelating agents with different stability constants with a metal source are used to complex base metal such as copper which dissolves into solution, if any. A fluorosurfactant is used as a wetting agent and stabilizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.