Method for integration of silicide contacts and silicide gate metals
US6927117B2 · kind B2 · utility
8Cited by
14References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Feb 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0174
Abstract
A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated with fabricating a CMOS structure containing silicide contacts and silicide gate metals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.